1. Field of the Invention
The disclosure relates generally to data transmission, and, more particularly to data transmission methods requesting specific length and address aligned bursts.
2. Description of the Related Art
Data transmission of memory is a key index of the performance of a computer system. It is a challenge for the hardware designer to improve the efficiency of the data transmission. For example, the operation software is used as the virtual address to indicate where the data are stored. Such a virtual address is mapped to a corresponding physical address which indicates where the data is in the hardware (memory). For the security and other reason, a data stored in the continuous virtual addresses may be divided to several data blocks which are mapped into different physical addresses. These data blocks are arranged randomly in the memory. It will cause more tasks to access such the data stored in the continuous virtual addresses and reduce the efficient in data transmission.
For example, the data transmission abovementioned is participated in the Advanced Microcontroller Bus Architecture (AMBA) which defines an on-chip bus standard. In AMBA, a variety of system components comprising a controller, memory and peripheral interfaces and others is coupled with buses thereon. In AMBA, high bandwidth buses such as Advanced High-performance Buses (AHB) are provided for data transfer between a plurality of masters and slaves. For example, a controller (master) can access a device (slave) such as memory via AHB. The device is a DMA (Direct Memory Access) type device supporting burst and pipelined data transfer procedures.
A data transfer procedure comprises grant, address/control and data cycles. In the grant cycle, a master first requests access to the bus, and an arbiter receives a request from the master and grants a master access to the master for transfer operations on the bus. In the address and control cycle, transfer information such as start address, direction and size for the transfer, and corresponding packet type are communicated, and data is presented in the data cycle. For example, one of the masters is granted to own the bus. The granted master can send data through the bus to a slave (write operation), or request a burst of data through the bus from a slave in an opposite direction (read operation). Similarly, one of the slaves is granted to own the bus. The granted slave can send data to be read by a master requesting the data.
Conventionally, if data with a specific length is requested, where the start address of the data is not address aligned (not on the double-word boundary (4DW/8DW/16DW)) from a memory, the master may use an unspecified length burst to request the data from the memory. Since the start address of the data is not address aligned, the master will request a burst across the address boundary, reducing the access performance. Since no length information is provided by the unspecified length burst, the slave efficiency is decreased. Additionally, the master may use more specified length bursts to request the data from the memory. The master must split a request into several small requests, reducing the efficiency of the bus. Similarly, since the start address of the data is not address aligned, the master will request a burst across the address boundary, reducing the access performance.